This invention relates generally to CMOS output buffer circuits and more particularly, it relates to a CMOS output buffer circuit employing an N-channel pull-up transistor with reduced body effect.
As is well-known in the art, digital logic circuits are widely used in the areas of electronics and computer-type equipment. Specifically, one such use of digital logic circuits is to provide an interface function between one logic type of a first integrated circuit device and another logic type of a second integrated logic device. An output buffer circuit is an important component for this interface function so as to render the two different logic types to be compatible. The output buffer circuit provides, when enabled, an output signal which is a function of a data input signal received from other logic circuitry of the integrated circuit.
Output buffer circuits typically use a pull-up transistor device connected between an upper power supply potential and an output node, and a pull-down transistor device connected between a lower power supply potential and the output node. Dependent upon the logic state of the data input signal and an enable signal, either the pull-up or pull-down transistor device is quickly turned on and the other one of them is turned off. When the enable signal is not asserted, the output node will be at a high impedance state referred to sometimes as the tri-state mode.
Sometimes, a P-channel device is provided so as to function as the pull-up device for generating a high output voltage level V.sub.OH corresponding to the high logic level. However, in applications which require the high drive capability the P-channel pull-up devices have been replaced with N-channel devices because their intrinsic mobility is more than twice than that of the P-channel device. With its greater mobility, the N-channel device is twice as conductive as compared to the P-channel device of an equal size. Due to its greater conduction, the N-channel device will have only half of the impedance between the drain terminal and the source terminal than an equivalent P-channel device. When such N-channel devices are utilized as the pull-up devices, they operate like source followers. In other words, the source electrode of the N-channel devices will attempt to follow the voltage at its gate electrode. The only disadvantage in using the N-channel devices is that the source electrode can only be pulled up to a voltage which is a threshold drop below the gate voltage.
Nevertheless, in the typical output buffer circuits the requirement is usually to pull the output node to a TTL (transistor-transistor-logic) level of only approximately +2.4 volts. With the upper power supply potential of +5.0 volts connected to its drain and its gate driven to +5.0 volts, the N-channel pull-up transistor can not achieve this TTL level if the effective threshold V.sub.Tn of such N-channel transistor is greater than +1.0 volts. Since the effective threshold V.sub.Tn is dependent upon the potential applied between the source and the substrate of the transistor referred sometimes to as the "body effect," transistors having a high "gamma" may fail to pull the output node to the desired TTL level due to saturation. One of the ways in which to overcome this problem is to tie the local substrate (P-well) of the N-channel transistor to its source region, thereby rendering the body effect to be zero. Further, a P-channel transistor is sometimes also connected in parallel with the N-channel pull-up transistor for facilitating the pull-up operation of the output node. In fact, such P-channel pull-up transistors can indeed pull the output node all the way up to the supply potential VCC if sufficient time is allowed for the operation.
However, the N-channel pull-up transistor having its source tied to its substrate and operated in the manner described above could possibly encounter certain problems. These problems can primarily be seen when the output buffer circuits are operated in the tri-state mode. In VLSI technology, there may be provided many output buffer circuits each having its output node tied together to a common I/O bus line with only one of the buffer circuits being active at one time. Under these circumstances, the single active output buffer circuit driving such common bus line will see a heavy loading effect caused by the additional parasitic capacitances of the collective P-wells of all of the remaining output buffer circuits which are in the tri-state mode.
Another problem encountered by such output buffer circuits is the power supply noise being coupled to the common bus line through one or more of the buffer circuits operated in the tri-state mode. If the output node of the active buffer circuit is required to be held close to the power supply level of VCC corresponding to the high logic state, the noise induced on the internal power supply node may degrade the output voltage level causing interface problems among the output buffer circuits and other integrated circuits. This noise also may cause the internal power supply node to undershoot the VCC level, which will cause the P-N diode between the P-well tied to the common bus line and the drain of the N-channel pull-up transistor to be forward biased and thus directly coupling the noise on the internal power supply node to the common bus line.
It would therefore be desirable to provide a CMOS output buffer circuit employing an N-channel pull-up transistor with reduced body effect. This is achieved in the present invention by a coupling transistor and a discharging transistor so as to control coupling and decoupling of the P-well of the N-channel pull-up transistor.